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XiangShan (open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) has improper gating of its distributed CSR write-enable path, allowing illegal CSR write attempts to alter custom PMA (Physical Memory Attribute) CSR state. Though the RISC-V privileged specification requires an illegal-instruction exception for non-existent/illegal CSR accesses, affected XiangShan versions may still propagate such writes to replicated PMA configuration state. Local attackers able to execute code on the core (privilege context depends on system integration) can exploit this to tamper with memory-attribute enforcement, potentially leading to privilege escalation, information disclosure, or denial of service depending on how PMA enforces platform security and isolation boundaries.

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XiangShan 安全漏洞

XiangShan是中国XiangShan开源的一个开源高性能RISC-V处理器项目。 XiangShan存在安全漏洞，该漏洞源于分布式CSR写使能路径门控不当，可能导致本地攻击者篡改内存属性，进而造成权限提升、信息泄露或拒绝服务。

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