Goal Reached Thanks to every supporter — we hit 100%!

Goal: 1000 CNY · Raised: 1359 CNY

100%

CWE-1276 — Vulnerability Class 1

1 vulnerabilities classified as CWE-1276. AI Chinese analysis included.

MITRE CWE Description
Signals between a hardware IP and the parent system design are incorrectly connected causing security risks. Individual hardware IP must communicate with the parent system in order for the product to function correctly and as intended. If implemented incorrectly, while not causing any apparent functional issues, may cause security issues. For example, if the IP should only be reset by a system-wide hard reset, but instead the reset input is connected to a software-triggered debug mode reset (which is also asserted during a hard reset), integrity of data inside the IP can be violated.
Common Consequences (1)
Confidentiality, Integrity, Availability Varies by Context
Mitigations (1)
Testing System-level verification may be used to ensure that components are correctly connected and that design security requirements are not violated due to interactions between various IP blocks.
Examples (2)
Many SoCs use hardware to partition system resources between trusted and untrusted entities. One example of this concept is the Arm TrustZone, in which the processor and all security-aware IP attempt to isolate resources based on the status of a privilege bit. This privilege bit is part of the input interface in all TrustZone-aware IP. If this privilege bit is accidentally grounded or left unconne…
// IP definition module tz_peripheral(clk, reset, data_in, data_in_security_level, ...); input clk, reset; input [31:0] data_in; input data_in_security_level; ... endmodule // Instantiation of IP in a parent system module soc(...) ... tz_peripheral u_tz_peripheral( .clk(clk), .rst(rst), .data_in(rdata), //Copy-and-paste error or typo grounds data_in_security_level (in this example 0=secure, 1=non-secure) effectively promoting all data to "secure") .data_in_security_level(1'b0), ); ... endmodule
Bad · Verilog
// Instantiation of IP in a parent system module soc(...) ... tz_peripheral u_tz_peripheral( .clk(clk), .rst(rst), .data_in(rdata), // This port is no longer grounded, but instead driven by the appropriate signal .data_in_security_level(rdata_security_level), ); ... endmodule
Good · Verilog
Here is a code snippet from the Ariane core module in the HACK@DAC'21 Openpiton SoC [REF-1362]. To ensure full functional correctness, developers connect the ports with names. However, in some cases developers forget to connect some of these ports to the desired signals in the parent module. These mistakes by developers can lead to incorrect functional behavior or, in some cases, introduce se…
... csr_regfile #( ... ) csr_regfile_i ( .flush_o             ( flush_csr_ctrl ), .halt_csr_o          ( halt_csr_ctrl ), ... .irq_i(), .time_irq_i(), .* ); ...
Bad · Verilog
... csr_regfile #( ... ) csr_regfile_i ( .flush_o             ( flush_csr_ctrl ), .halt_csr_o          ( halt_csr_ctrl ), ... .irq_i			(irq_i), .time_irq_i	(time_irq_i), .* ); ...
Good · Verilog

Vulnerabilities classified as CWE-1276 represent 1 CVEs. The CWE taxonomy describes the weakness; review individual CVEs for product-specific impact.