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CWE-1280 — Vulnerability Class 3

3 vulnerabilities classified as CWE-1280. AI Chinese analysis included.

MITRE CWE Description
A product's hardware-based access control check occurs after the asset has been accessed. The product implements a hardware-based access control check. The asset should be accessible only after the check is successful. If, however, this operation is not atomic and the asset is accessed before the check is complete, the security of the system may be compromised.
Common Consequences (1)
Access Control, Confidentiality, Integrity Modify Memory, Read Memory, Modify Application Data, Read Application Data, Gain Privileges or Assume Identity, Bypass Protection Mechanism
Mitigations (1)
Implementation Implement the access control check first. Access should only be given to asset if agent is authorized.
Examples (1)
Assume that the module foo_bar implements a protected register. The register content is the asset. Only transactions made by user id (indicated by signal usr_id) 0x4 are allowed to modify the register contents. The signal grant_access is used to provide access.
module foo_bar(data_out, usr_id, data_in, clk, rst_n); output reg [7:0] data_out; input wire [2:0] usr_id; input wire [7:0] data_in; input wire clk, rst_n; wire grant_access; always @ (posedge clk or negedge rst_n) begin if (!rst_n) data_out = 0; else data_out = (grant_access) ? data_in : data_out; assign grant_access = (usr_id == 3'h4) ? 1'b1 : 1'b0; end endmodule
Bad · Verilog
always @ (posedge clk or negedge rst_n) begin if (!rst_n) data_out = 0; else assign grant_access = (usr_id == 3'h4) ? 1'b1 : 1'b0; data_out = (grant_access) ? data_in : data_out; end endmodule
Good · Verilog

Vulnerabilities classified as CWE-1280 represent 3 CVEs. The CWE taxonomy describes the weakness; review individual CVEs for product-specific impact.